The present invention relates in general to test systems for integrated circuits (ICs), and in particular, to IC stress systems employing bum-in stress methods to facilitate early product life failures.
Bum-in stress is a method where an IC device is subjected to stress level operating conditions for the purpose of accelerating early failures that may occur when the IC device is assembled in a product. Burn-in stress generally involves elevating the temperature of an IC device beyond normal operating conditions and electrically exercising the IC device. There have been at times two opposing philosophies relating to burn-in. One philosophy is that bum-in eliminates weak IC devices resulting in a remaining set of robust IC devices. In this philosophy, burn-in is done to improve reliability and quality of IC devices being manufactured or used. The military, medical, and avionics are industries that have employed burn-in for this reason. There is a second philosophy of burn-in testing which contends that stressing a group of IC devices may weed out weak IC devices but it also weakens the IC devices that do not fail and thus reduces the quality of the remaining IC devices. Practitioners of the second philosophy of bum-in sometimes prefer to use burn-in as a way to improve the manufacturing process of a particular IC device. IC devices are stressed to failure, the failures are analyzed, and the results of the analysis are used to modify the manufacturing process. Once the process is optimized, manufactured IC devices are no longer subjected to burn-in stresses.
If burn-in is done to improve the quality of surviving IC devices, bum-in stress may be required on all production IC devices. This results in the need for burn-in chambers where a large number of IC devices can be stressed at one time typically using the same stress parameter profiles. Special bum-in boards (stress motherboards) are used to facilitate this stressing. These burn-in stress chambers many times subject the entire stress motherboard to burn-in stress conditions including the circuit board and the support circuitry. Sometimes the electrical environment presented by these burn-in stress motherboards deviates considerably from the environment experienced in the field. If the IC device under stress is a processor chip, the additional support ICs necessary for the processor chip to operate may not be present in these prior art bum-in stress systems and therefore the processor chip undergoes stresses of burn-in within a non-application system circuit environment. Many traditional burn-in methods apply electrical stimuli to many IC devices simultaneously and thus the signal frequency is lower than the IC device would normally experience in a product environment.
It is desirable to operate an IC device with its normal support circuitry and normal operational modes as it ensures circuit nodes within the IC device are extensively exercised during burn-in. One of the features of burn-in stress is the elevation of the IC device operating temperature simultaneous with the IC device circuit nodes experiencing voltage transitions. The rate of the voltage transitions (operating frequency) on the circuit nodes of an IC device during burn-in also adds to burn-in stress levels and is important to accelerating early life failures.
While it may be desirable to burn-in particular IC devices, it may not be desirable for all the chips in its support chip set to undergo the same stress levels or profiles during burn-in. There is also a need for the burn-in environment to allow the IC devices being stressed to be maintained in a circuit environment like the one experienced in a product level application.
An IC device system level burn-in method and apparatus are disclosed which enable IC devices to undergo burn-in within a circuit environment like the one experienced in a product level application. A bum-in stress motherboard has sockets for multiple IC devices along with support chip-sets and a stress controller. A stress software program, executing on the controller, controls IC device voltage, temperature, and operating frequency. Each IC device under stress has an individual cooling means and corresponding temperature controllers. IC device temperature is elevated by self heating and controlled by the temperature controller which uses set point data from the stress software program. The IC devices execute system code or Built In Self Test (BIST) code during bum-in. Burn-in operational parameters are customized for each IC device under stress. A support chip-set coupled to an IC device provides field level circuitry to stress the IC device. The IC device system level burn-in does not stress any unessential components during stress of a particular IC device.
Multiple stress motherboards each with multiple IC devices may be grouped into larger stress systems. Since each stress motherboard has its own stress controller, each stress motherboard may have different IC device types. The parameter profiles and the stress sequences for the particular IC device parts are controlled by the stress software program and easily modified to accommodate different part numbers.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.